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november 2007 hyb25dc128800c[e/f] hyb25dc128160c[e/f] 128-mbit double-data-rate sdram ddr sdram internet data sheet rev. 1.12
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com data sheet hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram qag_techdoc_rev400 / 3.2 qag / 2006-08-01 2 03062006-jxuk-e7r1 hyb25dc128800c[e/f], hyb25dc128160c[e/f] revision history: 2007-11 , rev. 1.12 page subjects (major chan ges since last revision) all adapted internet version all update images previous revision: 2007-10, rev 1.11 all update ballsize previous revision: 2007-01, rev 1.10 all quimonda update previous revision: 2005-07, rev 1.00
data sheet rev. 1.12, 2007-11 3 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 1overview this chapter lists all main features of the product fa mily hyb25dc128[800/160]c[e/f] and the ordering information. 1.1 features ? double data rate architecture: tw o data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 2, 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap = t rcd ? 15.6 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ? v ddq = 2.5 v 0.2 v ? v dd = 2.5 v 0.2 v ? pg-tfbga-60 package with 3 depopulated rows (8 12 mm 2 ) ? pg-tsopii-66 package ? lead- and halogene-free = green product table 1 performance the 128-mbit double-data-rate sdram is a high-speed cmos, dynamic random-access memory containing 134,217,728 bits. it is internally co nfigured as a quad-bank dram. the 128-mbit double-data-rate sdram uses a double-data-rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 128-mbit double-data-rate sdram effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal dra m core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. part number speed code ?5 ?6 unit speed grade component ddr400b ddr333 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz
data sheet rev. 1.12, 2007-11 4 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capt ure at the receiver. dqs is a strobe transmitted by the during reads and by the memory co ntroller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 128-mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). co mmands (address and control signal s) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is refe renced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented ; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the addr ess bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst le ngths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at t he end of the burst access. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams al lows for concurrent operation, thereby providing high effective bandwidth by hi ding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all in puts are compatible with the industry standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timi ng specifications included in this dat a sheet are for the dll enabled mode of operation. table 2 order information for rohs compliant products part number 1) 1) hyb: designator for memory components 25dc: s at v ddq = 2.5 v 128: 128-mbit density 800/160: product variations 8 and 16 c: die revision c f/e: package type tsop and fbga l: low power version (available on request) - t hese components are specifically selected for low i dd6 self refresh currents -5, - 6: speed grade org. cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) speed package note hyb25dc128800ce-5 8 3-3-3 200 2.5-3-3 166 ddr400b pg-tsopii-66 2) 2) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament an d of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. hyb25dc128160ce-5 16 HYB25DC128160CF-5 16 pg-tfbga-60 hyb25dc128800ce?6 8 2.5-3-3 166 2-3-3 133 ddr333b pg-tsopii-66 hyb25dc128160ce?6 16 hyb25dc128800cf?6 8 pg-tfbga-60 hyb25dc128160cf?6 16
data sheet rev. 1.12, 2007-11 5 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 2 pin configuration the pin configuration of a ddr sdram is listed by function in table 3 (60 pins). the abbreviations used in the pin#/buffer# column are explained in table 4 and table 5 respectively. the pin numbering for fbga is depicted in figure 1 and that of the tsop package in figure 2 . table 3 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals g2, 45 ck i sstl clock signal note: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). g3, 46 ck i sstl complementary clock signal h3, 44 cke i sstl clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffers, excluding cke, are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied on first power up. after v ref has become stable during the power on and initialization sequence, it must be mantained for proper operation of the cke receiver. for proper self- refresh entry and exit, v ref must be mantained to this input. control signals h7, 23 ras i sstl row address strobe g8, 22 cas i sstl column address strobe g7, 21 we i sstl write enable h8, 24 cs i sstl chip select note: all commands are masked when cs is registered high. cs provides for external bank se lection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. address signals j8, 26 ba0 i sstl bank address bus 2:0 note: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. j7, 27 ba1 i sstl
data sheet rev. 1.12, 2007-11 6 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram k7, 29 a0 i sstl address bus 11:0 l8, 30 a1 i sstl l7, 31 a2 i sstl m8, 32 a3 i sstl m2, 35 a4 i sstl l3, 36 a5 i sstl l2, 37 a6 i sstl k3, 38 a7 i sstl k2, 39 a8 i sstl j3, 40 a9 i sstl k8, 28 a10 i sstl ap i sstl j2, 41 a11 i sstl h2, 42 a12 i sstl address signal 12 note: 256 mbit or larger dies nc nc ? note: 128 mbit or smaller dies f9, 17 a13 i sstl address signal 13 note: 1 gbit based dies nc nc ? note: 512 mbit or smaller dies data signals 8 organization a8, 2 dq0 i/o sstl data signal 7:0 b7, 5 dq1 i/o sstl c7, 8 dq2 i/o sstl d7, 11 dq3 i/o sstl d3, 56 dq4 i/o sstl c3, 59 dq5 i/o sstl data signal b3, 62 dq6 i/o sstl a2, 65 dq7 i/o sstl data strobe 8 organisation e3, 51 dqs i/o sstl data strobe data mask 8 organization f3, 47 dm i sstl data mask ball#/pin# name pin type buffer type function
data sheet rev. 1.12, 2007-11 7 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram data signals 16 organization a8, 2 dq0 i/o sstl data signal 15:0 b9, 4 dq1 i/o sstl b7, 5 dq2 i/o sstl c9, 7 dq3 i/o sstl c7, 8 dq4 i/o sstl d9, 10 dq5 i/o sstl d7, 11 dq6 i/o sstl e9, 13 dq7 i/o sstl e1, 54 dq8 i/o sstl d3, 56 dq9 i/o sstl d1, 57 dq10 i/o sstl c3, 59 dq11 i/o sstl c1, 60 dq12 i/o sstl b3, 62 dq13 i/o sstl b1, 63 dq14 i/o sstl a2, 65 dq15 i/o sstl data strobe 16 organization e3, 51 udqs i/o sstl data strobe upper byte e7, 16 ldqs i/o sstl data strobe lower byte data mask 16 organization f3, 47 udm i sstl data mask upper byte f7, 20 ldm i sstl data mask lower byte power supplies f1, 49 v ref ai ? i/o reference voltage a9, b2, c8, d2, e8, 3, 9, 15, 55, 61 v ddq pwr ? i/o driver power supply a7, f8, m7, 1, 18, 33 v dd pwr ? power supply a1, b8, c2, d8, e2, 6, 12, 52, 58, 64 v ssq pwr ? power supply a3,f2, m3, 34, 48, 66, v ss pwr ? power supply not connected a2, 65 nc nc ? not connected note: 4 organization a8, 2 nc nc ? not connected note: 4 organization b1, 63 nc nc ? not connected note: 8 and 4 organisation ball#/pin# name pin type buffer type function
data sheet rev. 1.12, 2007-11 8 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 4 abbreviations for pin type b9, 4 nc nc ? not connected note: 8 and 4 organization c1, 60 nc nc ? not connected note: 8 and 4 organization c3, 59 nc nc ? not connected note: 4 organization c7, 8 nc nc ? not connected note: 4 organization c9, 7 nc nc ? not connected note: 8 and 4 organization d1, 57 nc nc ? not connected note: 8 and 4 organization d9, 10 nc nc ? not connected note: 8 and 4 organization e1, 54 nc nc ? not connected note: 8 and 4 organization e7, 16 nc nc ? not connected note: 8 and 4 organization e9, 13 nc nc ? not connected note: 8 and 4 organization f7, 20 nc nc ? not connected note: 8 and 4 organization f9, 14, 17, 19, 25,43, 50, 53 nc nc ? not connected note: 16, 8 and 4 organization abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nc not connected ball#/pin# name pin type buffer type function
data sheet rev. 1.12, 2007-11 9 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 5 abbreviations for buffer type figure 1 pin configuration pg-tfbga-60 top vi ew, see the balls through the package abbreviation description sstl serial stub terminated logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operat ional states, active low and tristate, and allows multiple devices to share as a wire-or. 033+ '08 $ 9 664 %$ 9 66 '48 '4/ '48 9 ''4 '48 9 664 9 5()'4 9 66 9 664 $ '/4 $ 9 66 $ 9 '' $ % & ' ) * + - ( / 0 . 1 9 ''4 2'7 %$ %$ 9 66 9 ''4 $%$ 9 5()&$ 9 66 9 '' $ $ $ 9 664 $ 9 66 9 '' 9 66 9 '' 5(6(7 $ 3 5 7 $ $ $ $ 9 66 9 ''4 '48 9 '' 9 66 9 664 '4/ 9 ''4 '4/ '46/ 9 664 '4/ '46/ 9 ''4 '4/ 1& 9 66 5$6 9 '' &$6 1& &6 :( $ 9 '' 9 ''4 '48 '468 '48 '468 '48 '0/ 9 664 9 '' '48 9 ''4 '4/ 9 664 9 664 '/4 9 ''4 9 66 &. 9 66 1& &. 9 '' &.( $$3 =4 1&
data sheet rev. 1.12, 2007-11 10 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram figure 2 pin configuration pg-tsopii-66 033' 9 '' '4 9 ''4 9 664 '4 '4 9 ''4 '4 '4 '4 '4 9 664 '4 9 ''4 1& /'46 1&$ 9 '' 1& /'0 :( &$6 5$6 &6 1& %$ %$ $$3 $ $ $ $ 9 '' 9 '' '4 9 ''4 9 664 1& '4 9 ''4 1& '4 1& '4 9 664 1& 9 ''4 1& 1& 1&$ 9 '' 1& 1& :( &$6 5$6 &6 1& %$ %$ $$3 $ $ $ $ 9 '' 9 66 '4 9 664 9 ''4 '4 '4 9 664 '4 '4 '4 '4 9 ''4 '4 9 664 1& 8'46 1& 9 5() 8'0 &. &. &.( 1& 1&$ $ $ $ $ $ $ $ 9 66 9 66 9 66 '4 9 664 9 ''4 1& '4 9 664 1& '4 1& '4 9 ''4 1& 9 664 1& '46 1& 9 5() '0 &. &. &.( 1& 1&$ $ $ $ $ $ $ $ 9 66 9 66 [ [
data sheet rev. 1.12, 2007-11 11 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 3 functional description the 128-mbit double-data-rate sdram is a high-speed cmos, dynamic random-access memory containing 134,217,728 bits. the 128-mbit double-data-rate sdram is internally configured as a quad-bank dram. the 128-mbit double-data-rate sdram uses a double-data-rate ar chitecture to achieve high-speed operation. the double- data-rate architecture is essentially a 2n prefetch architecture, with an interfac e designed to transfer two data words per clo ck cycle at the i/o pins. a single read or write access for the 128-mbit double-data-rate sdram consists of a single 2n-bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented ; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the addr ess bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram mu st be initialized. the fo llowing sections provide detailed information covering device initialization, regist er definition, command descriptions and device operation.
data sheet rev. 1.12, 2007-11 12 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 6 mode register definition field bits type 1) 1) w = write only register bit description bl [2:0] w burst length number of sequential bits per dq related to one read/write command. note: all other bit combinations are reserved. 001 b 2 010 b 4 011 b 8 bt 3 burst type see table 7 for internal address sequence of low order address bits. 0 sequential 1 interleaved cl [6:4] cas latency number of full clocks from read command to first data valid window. note: all other bit combinations are reserved. 010 b 2 011 b 3 110 b 2.5 101 b 1.5 note: cl = 1.5 for ddr200 components only mode [11:7] operating mode note: all other bit combinations are reserved. 000000 normal operation without dll reset 000010 normal operation with dll reset 03%' %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ 02'( %/ &/ %7 uhjdggu zzzz
data sheet rev. 1.12, 2007-11 13 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 7 extended mode register field bits type 1) 1) w = write only register bit description dll 0w dll status 0 b enabled 1 b disabled ds 1 drive strength 0 b normal 1 b weak mode [11:2] operating mode 0000000000 b normal operation notes 1. a2 must be 0 to provide compatibility with early ddr devices 2. all other bit comb inations are reserved 03%' %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ 02'( '6 '//
data sheet rev. 1.12, 2007-11 14 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 8 truth table 1a: commands table 9 truth table 1b: dm operation name (function) cs ras cas we address mne note deselect (nop) h x x x x nop 1)2) 1) cke is high for all commands shown except self refresh. v ref must be maintained during self refresh operation 2) deselect and nop are functionally interchangeable. no operation (nop) l h h h x nop 1)2) active (select bank and activate row) l l h h bank/row act 1)3) 3) ba0-ba1 provide bank address and a0-a11 provide row address. read (select bank and column, and start read burst) l h l h bank/col read 1)4) 4) ba0, ba1 provide bank address; a0-ai provide column address (where i = 8 for x16, i = 9 for x8 ); a10 high enables the auto precharge feature (nonpersist ent), a10 low disables the auto precharge feature. write (select bank and column, and start write burst) l h l l bank/col write 1)4) burst terminate l h h l x bst 1)5) 5) applies only to read bursts with auto precharge disabled; th is command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts. precharge (deactivate row in bank or banks) l l h l code pre 1)6) 6) a10 low: ba0, ba1 determ ine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. auto refresh or self refresh (e nter self refresh mode) l l l h x ar/sr 1)7)8) 7) this command is auto refresh if cke is high; self refresh if cke is low. 8) internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. mode register set l l l l op-code mrs 1)9) 9) ba0, ba1 select either the base or the extended mode register ( ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserv ed; a0-a11 provide the op-code to be written to the selected mo de register). name (function) dm dqs note write enable lvalid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit hx
data sheet rev. 1.12, 2007-11 15 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 10 truth table 2: clock enable (cke) notes 1. cken is the logic state of cke at clock edge n: ck e n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. table 11 truth table 3: current state bank n - command to bank n (same bank) current state cke n-1 cken command n action n note previous cycle current cycle self refresh l l x maintain self-refresh 1) 1) v ref must be maintained during self refresh operation self refresh l h deselect or nop exit self-refresh 2) 2) deselect or nop commands should be issued on any clock edges occurring during the self refresh exit ( t xsnr ) period. a minimum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock. power down l l x maintain power-down ? power down l h deselect or nop exit power-down ? all banks idle h l deselect or nop precharge power-down entry ? all banks idle h l auto refresh self refresh entry ? bank(s) active h l deselect or nop active power-down entry ? hhsee table 11 ?? current state cs ras cas we command action note any hxxxdeselect nop. continue previous operation. 1)2)3)4)5)6) 1) this table applies when cke n-1 was high and cke n is high (see table 10 and after t xsnr / t xsrd has been met (if the previous state was self refresh). l hhhno operation nop. continue previous operation. 1) to 6) idle l l h h active select and activate row 1) to 6) lllhauto refresh? 1) to7) llllmode register set ? 1) to 7) row active l h l h read select column and start read burst 1) to 6),8) l h l l write select column and start write burst 1) to 6),8) l l h l precharge deactivate row in bank(s) 1) to 6),9) read (auto precharge disabled) l h l h read select column and start new read burst 1) to 6),8) l l h l precharge truncate read burst, start precharge 1) to 6),9) l hhl burst terminate burst terminate 1) to 6),10) write (auto precharge disabled) l h l h read select column and start read burst 1) to 6), 8),11) l h l l write select column and start write burst 1) to 6),8) l l h l precharge truncate write burst, start precharge 1) to 6),9),11)
data sheet rev. 1.12, 2007-11 16 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 12 truth table 4: current state bank n - command to bank m (different bank) 2) this table is bank-specific, ex cept where noted, i.e., the current state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminat ed. write: a write burst has been initiated, with auto prec harge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a command issu ed to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row ac tivating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with regist ration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or no p commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable co mmands to the other bank are determined by its current stat e and according to table 12 . 5) the following states must not be interrupted by any executab le command; deselect or nop commands must be applied on each posi tive clock edge during these states. refres hing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set co mmand and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6) all states and sequences not shown are illegal or reserved. 7) not bank-specific; requires that all banks are idle. 8) reads or writes listed in the command/action column include read s or writes with auto precharge enabled and reads or writes w ith auto precharge disabled. 9) may or may not be bank-specific; if al l/any banks are to be precharged, all/any must be in a valid state for precharging. 10) not bank-specific; burst terminate affects th e most recent read burst, regardless of bank. 11) requires appropriate dm masking. current state cs ras cas we command action note any hxxxdeselect nop. continue previous operation. 1)2)3)4)5)6) l hhhno operation nop. continue previous operation. 1) to 6) idle xxxxany command otherwise allowed to bank m ? 1) to 6) row activating, active, or precharging l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to7) l h l l write select column and start write burst 1) to 7) llhlprecharge ? 1) to 6) read (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7) llhlprecharge ? 1) to 6) write (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to8) l h l l write select column and start new write burst 1) to 7) llhlprecharge ? 1) to 6)
data sheet rev. 1.12, 2007-11 17 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 13 truth table 5: concurrent auto precharge read (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7),9) l h l l write select column and start write burst 1) to 7),9),10) llhlprecharge ? 1) to 6) write (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7),9) l h l l write select column and start new write burst 1) to 7),9) llhlprecharge ? 1) to 6) 1) this table applies when cke n-1 was high and cke n is high (see table 10 : clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table describes alternate bank operat ion, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are co vered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminat ed. write: a write burst has been initiated, with auto prec harge disabled, and has not yet terminated or been term inated. read with auto precharge enabled: see 10) . write with auto precharge enabled: see 10) . 4) auto refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) all states and sequences not shown are illegal or reserved. 7) reads or writes listed in the command/action column include read s or writes with auto precharge enabled and reads or writes w ith auto precharge disabled. 8) requires appropriate dm masking. 9) concurrent auto precharge: this device supports ?concurrent auto precharge?. when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as l ong as that command does not interrupt the read or write dat a transfer and all other limitations apply (e.g. contention between read data and write data must be avoided). the minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 13 . 10) a write command may be applied after the completion of data output. from command to command (different bank) minimum delay with concurrent auto precharge support unit write w/ap read or read w/ap 1 + (bl/2) + t wtr t ck write to write w/ap bl/2 t ck precharge or activate 1 t ck read w/ap read or read w/ap bl/2 t ck write or write w/ap cl (rounded up) + bl/2 t ck precharge or activate 1 t ck current state cs ras cas we command action note
data sheet rev. 1.12, 2007-11 18 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 4 electrical characteristics 4.1 operating conditions table 14 absolute maximum ratings attention: stresses above the max. value s listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 15 input and output capacitances parameter symbol values unit min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v voltage on inputs relative to v ss v in ?1 ? +3.6 v voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v operating temperature (ambient) t a 0?+70 c storage temperature (plastic) t stg ?55 ? +150 c power dissipation (per sdram component) p d ?1 ? w short circuit output current i out ?50? ma parameter symbol values unit note/ test condition min. typ. max. input capacitance: ck, ck c i1 2.0 ? 3.0 pf tsopii 1) 1) these values are guaranteed by design and are tested on a sample base only. v ddq = v dd = 2.5 v 0.2 v, f = 100 mhz, t a = 25 c, v out(dc) = v ddq /2, v out (peak to peak) 0.2 v. unused pins are tied to ground. 1.5 ? 2.5 pf tfbga 1) delta input capacitance c di1 ? ? 0.25 pf 1) input capacitance: all other input-only pins c i2 1.5 ? 2.5 pf tfbga 1) 2.0 ? 3.0 pf tsopii 1) delta input capacitance: all other input-only pins c dio ?? 0.5pf 1) input/output capacitance: dq, dqs, dm c io 3.5 ? 4.5 pf tfbga 1)2) 2) dm inputs are grouped with i/o pins reflecting the fact that t hey are matched in loading to dq and dqs to facilitate trace ma tching at the board level. 4.0 ? 5.0 pf tsopii 1)2) delta input/output capaci tance: dq, dqs, dm c dio ?? 0.5pf 1)
data sheet rev. 1.12, 2007-11 19 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 16 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v; min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck > 166 mhz 2) 2) ddr400 conditions apply for all clock frequencies above 166 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) 3) under all conditions, v ddq must be less than or equal to v dd . output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) 4) peak to peak ac noise on v ref may not exceed 2% v ref.dc . v ref is also expected to tr ack noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 6) 6) inputs are not recognized as valid until v ref stabilizes. input low (logic0) voltage v il(dc) ? 0.3 v ref ? 0.15 v 6) input voltage level, ck and ck inputs v in(dc) ? 0.3 v ddq + 0.3 v 6) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 6)7) 7) v id is the magnitude of the difference between the input level on ck and the input level on ck . vi-matching pull-up current to pull-down current v i ratio 0.71 1.4 ? 8) 8) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1. 0 v. for a given output, it represents the maximum difference b etween pull-up and pull-down drivers due to process variation. input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test = 0 v 9) 9) values are shown per pin. output leakage current i oz ?5 5 a dqs are disabled; 0 v v out v ddq 9) output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v
data sheet rev. 1.12, 2007-11 20 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 4.2 normal strength pull-down and pull-up characteristics this chapter contains the normal strengt h pull-down and pull-up characteristics. 1. the nominal pull-down v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 2. the full variation in driver pull-down current from minimum to maximum process, temperatur e, and voltage lie within the outer bounding lines of the v - i curve. 3. the nominal pull-up v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 4. the full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 5. the full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 v. figure 3 normal strength pull- down characteristics 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 i out (ma) v out (v) maximum nominal high nominal low minimum
data sheet rev. 1.12, 2007-11 21 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram figure 4 normal strength pull-up characteristics maximum nominal high nominal low minimum v ddq - v out (v) 0.5 1 1.5 2 2.5 0 0 -20 -40 -60 -80 -100 -120 -140 -160 i out (ma)
data sheet rev. 1.12, 2007-11 22 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 17 normal strength pull-do wn and pull-up currents table 18 pull-down and pull-up process variations and conditions voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 - 51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 - 51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 - 51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 - 51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 - 51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 - 51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 - 52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 - 52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 - 52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 - 52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 - 52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 - 52.8 -160.1 -41.2 -198.2 parameter nominal minimum maximum operating temperature 25 c0 c 70 c v dd / v ddq 2.5 v 2.3 v 2.7 v
data sheet rev. 1.12, 2007-11 23 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 4.3 weak strength pull-down and pull-up characteristics this chapter contains the weak strengt h pull-down and pull-up characteristics. 1. the weak pull-down v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 2. the weak pull-up v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 3. the full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 4. the full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 v. figure 5 weak strength pull-do wn characteristics 0 10 20 30 40 50 60 70 80 0,00,51,01,52,02,5 vout [v] iout [ma] maxim um typical high typical low minim um
data sheet rev. 1.12, 2007-11 24 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram figure 6 weak strength pull-up characteristics -80,0 -70,0 -60,0 -50,0 -40,0 -30,0 -20,0 -10,0 0,0 0,0 0,5 1,0 1,5 2,0 2,5 vddq - v out [v] iout [ ma ] maximum typical high typical low minimum
data sheet rev. 1.12, 2007-11 25 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 19 weak strength driver pull-down and pull-up characteristics voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
data sheet rev. 1.12, 2007-11 26 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 4.4 ac characteristics (notes 1-5 apply to the following tables; electrical charac teristics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and elec trical characteristics and ac timing.) notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal re ference/supply voltage levels, but the related specifications and device oper ation are guaranteed for the full voltage range specified. 3. figure 7 represents the timing reference load used in defining the re levant timing parameters of the part. it is not intended to be either a precise representation of the typical system environm ent nor a depiction of the ac tual load presented by a production tester. system designers will use ibis or other simula tion tools to correlate the ti ming reference load to a system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5 v in the test environ ment, but input timing is still referenced to v ref (or to the crossi ng point for ck, ck ), and parameter spec ifications are guaranteed for t he specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1 v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e . the receiver effectively switches as a result of the signal crossing the ac input level, and remain s in that state as long as the signal does not ring back above (below) the dc input low (high) level). 6. for system characteristics like setup & holdtime derating for slew rate, i/o delta rise/ fall derating, ddr sdram slew rate standards, overshoot & unde rshoot specification and clamp v - i characteristics see the latest industry standard for ddr components. figure 7 ac output load circuit diagram / timing reference load 50 timing reference point output ( v out ) 30 pf v tt
data sheet rev. 1.12, 2007-11 27 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 20 ac operating conditions table 21 ac timing - absolute specifications parameter symbol values unit note/ test condition min. max. input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 ? v 1)2)3) 1) v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr200 - ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400); 0 c t a 70 c 2) input slew rate = 1 v/ns. 3) inputs are not recognized as valid until v ref stabilizes. input low (logic 0) voltage, dq, dqs and dm signals v il(ac) ? v ref ? 0.31 v 1)2)3) input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 1)2)3)4) 4) v id is the magnitude of the difference between the input level on ck and the input level on ck . input closing point voltage, ck and ck inputs v ix(ac) 0.5 v ddq ? 0.2 0.5 v ddq + 0.2 v 1)2)3)5) 5) the value of v ix is expected to equal 0.5 v ddq of the transmitting device and must track variations in the dc level of the same. parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.45 ns tsopii 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5)
data sheet rev. 1.12, 2007-11 28 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ? +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.7 +0.70 ?0.70 +0.70 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.55 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ? 15.6 ? 15.6 s 2)3)4)5)8) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre max. (0.25 t ck , 1.5 ns) ?0.25 t ck ?ns 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)10) parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
data sheet rev. 1.12, 2007-11 29 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 22 i dd conditions write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)11) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 10) the specific requirement is that dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a v alid transition is defined as monotonic and meeting the input slew rate specificationsof the device. w hen no writes were previously in progress on the bus, dqs will be transitioni ng from hi-z to logic low. if a previous write wa s in progress, dqs could be high, low at this time , depending on t dqss . 11) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. parameter symbol operating current: one bank; active/ precharge; t rc = t rcmin ; t ck = t ckmin ; dq, dm, and dqs inputs changing once per clock cycle ; address and control inputs changing once every two clock cycles. i dd0 operating current: one bank; active/read/precharge; burst = 4; refer to the following page for detailed test conditions. i dd1 precharge power-down standby current: all banks idle; power-down mode; cke v ilmax ; t ck = t ckmin i dd2p precharge floating standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other c ontrol inputs ch anging once per clock cycle, v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other control inputs stable at v ihmin or v ilmax ; v in = v ref for dq, dqs and dm. i dd2q active power-down standby current: one bank active; power-down mode; cke v ilmax ; t ck = t ckmin ; v in = v ref for dq, dqs and dm. i dd3p active standby current: one bank active; cs v ihmin ; cke v ihmin ; t rc = t rasmax ; t ck = t ckmin ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle i dd3n parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
data sheet rev. 1.12, 2007-11 30 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram operating current: one bank active; burst = 2; reads; continuo us burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin ; i out =0ma i dd4r operating current: one bank active; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin i dd4w auto-refresh current: t rc = t rfcmin , burst refresh i dd5 self-refresh current: cke 0.2 v; external clock on; t ck = t ckmin i dd6 operating current: four bank; four bank interleaving with bl = 4; refer to the following page for detailed test conditions. i dd7 parameter symbol
data sheet rev. 1.12, 2007-11 31 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 23 i dd specification symbol ?5 ?6 unit note/test condition 1) 1) test conditions: v dd = 2.7 v, t a = 10 c ddr400b ddr333b i dd0 90 75 ma 8 2)3) 2) i dd specifications are tested after the device is properly in itialized and measured at 133 mhz for ddr266, 166 mhz for ddr333, and 2 00 mhz for ddr400. 3) input slew rate = 1 v/ns. 90 75 ma 16 3) i dd1 100 85 ma 8 3) 110 95 ma 16 3) i dd2p 5 5ma 3) i dd2f 36 30 ma 3) i dd2q 28 24 ma 3) i dd3p 18 15 ma 3) i dd3n 45 38 ma 3) 54 45 ma 16 3) i dd4r 100 85 ma 8 3) 120 100 ma 16 3) i dd4w 105 90 ma 8 3) 130 110 ma 16 3) i dd5 190 160 ma 3) i dd6 3.0 3.0 ma 4) 4) enables on-chip refresh and address counters. ? 1.1 ma low power 5) 5) low power available on request i dd7 250 215 ma 8 3) 250 215 ma 16 3)
data sheet rev. 1.12, 2007-11 32 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 4.5 i dd current measurement conditions legend: a = activate, r = read, ra = read with au toprecharge, p = precharge, n = nop or deselect i dd1 : operating current: one bank operation 1. general test condition a) only one bank is accessed with t rc,min . b) burst mode, address and control inputs are changing once per nop and deselect cycle. c) 50% of data changing at every transfer d) i out = 0 ma. 2. timing patterns a) ddr266a (133 mhz, cl = 2): t ck = 7.5 ns, bl = 4, t rcd = 3 t ck , t rc = 9 t ck , t ras = 5 t ck setup: a0 n n r0 n p0 n n n read: a0 n n r0 n p0 n nn - repeat the same timing with random address changing b) ddr333b (166 mhz, cl = 2.5): t ck = 6 ns, bl = 4, = 3 t ck , t rc = 10 t ck , t ras = 7 t ck setup: a0 n n r0 n n n p0 n n read: a0 n n r0 n n n p0 n n - repeat t he same timing with random address changing c) ddr400b (200 mhz, cl = 3): t ck = 5 ns, bl = 4, t rcd = 3 t ck , t rc = 11 t ck , t ras = 8 t ck setup:a0 n n r0 n n n n p0 n n read: a0 n n r0 n n n n p0 n n -repeat the same timing with random address changing i dd7 : operating current: four bank operation 1. general test condition a) four banks are being interleaved with t rcmin . b) burst mode, address and control inputs on nop edge are not changing. c) 50% of data changing at every transfer d) i out = 0 ma. 2. timing patterns a) ddr266a (133 mhz, cl = 2): t ck = 7.5 ns, bl = 4, t rrd = 2 t ck , t rcd = 3 t ck , t ras = 5 t ck setup: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 read: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 - repeat the same timing with random address changing b) ddr333b (166 mhz, cl = 2.5): t ck = 6 ns, bl = 4, t rrd = 2 t ck , t rcd = 3 t ck , t ras = 5 t ck setup: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 read: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 - repeat the same timing with random address changing c) ddr400b (200 mhz, cl = 3): t ck = 5 ns, bl = 4, t rrd = 2 t ck , t rcd = 3 * t ck , t ras = 8 t ck setup: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n read: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n - repeat the same timing with random address
data sheet rev. 1.12, 2007-11 33 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 5 package outlines there are two package types used for this product family in lead-free assembly: ? pg-tsopii: plastic thin small outline package type ii ? pg-tfbga: plastic thin fine-p itch ball grid array package figure 8 package outline of pg-tsopii-66 table 24 tfbga common package properties description size units ball size 0.450 mm recommended landing pad 0.350 mm recommended solder mask 0.450 mm ' r h v q r w l q f o x g h s o d v w l f s u r w u x v l r q r i p d [ s h u v l g h ' r h v q r w l q f o x g h g d p e d u s u r w u x v l r q r i p d [ ' r h v q r w l q f o x g h s o d v w l f r u p h w d o s u r w u x v l r q r i p d [ s h u v l g h ? ? ? ? ? ? ? [ ? 0 [ 0 $; 0 $; , q g h [ 0 d u n l q j ? ? ? ? ? ? ? ? ? ? [ 6 ( $ 7, 1 * 3 /$1 ( ? ? 0 , 1 * $ 8 * ( 3 /$1 ( ) 3 2 b 3 b 7 6 2 3 , , b
data sheet rev. 1.12, 2007-11 34 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram figure 9 package outline of pg-tfbga-60 )32b3b7)%*$bb 0lggoh ri sdfndjhv hgjhv %dg xqlw pdunlqj %80 $ pdunlqj fklsvlgh $ pdunlqj edoovlgh 'xpp\ sdgv zlwkrxw edoo [ 0$; [ % $ 0$; 0$; 0,1 & ? ? ? ? [ 0 0 $ & & % 6($7,1* 3/$1( & &
data sheet rev. 1.12, 2007-11 35 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram figure 1 pin configuration pg-tfbga-60 top view, see the balls th rough the package . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 pin configuration pg-tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 normal strength pull-down characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4 normal strength pu ll-up characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5 weak strength pull-down characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6 weak strength pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7 ac output load circuit diagram / timing reference load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8 package outline of pg-tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9 package outline of pg-tfbga-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 list of figures
data sheet rev. 1.12, 2007-11 36 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2 order information for rohs compliant pr oducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3 pin configuration of ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6 mode register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8 truth table 1a: commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9 truth table 1b: dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10 truth table 2: clock enable (cke). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11 truth table 3: current state bank n - command to bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12 truth table 4: current state bank n - command to bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13 truth table 5: concurrent auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 15 input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 16 electrical characteristics and dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 17 normal strength pull-down and pull-up currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 18 pull-down and pull-up process variations and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 19 weak strength driver pull-down and pu ll-up characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21 ac timing - absolute specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22 i dd conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 23 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 24 tfbga common package properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 list of tables
data sheet rev. 1.12, 2007-11 37 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 normal strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 weak strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 i dd current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table of contents
edition 2007-11 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this data sheet shall in no event be regarded as a guarantee of co nditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com data sheet

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